? semiconductor components industries, llc, 2003 july, 2003 - rev. 0 1 publication order number: and8119/d prepared by: juan carlos pastrana on semiconductor introduction power converters using secondary side controllers provide better transient response, higher efficiency and usually require less components than their primary side referenced counterparts. however, secondary side controllers require a primary side referenced bias supply to start operation. after start-up, the controller power can be provided from the secondary side. the ncp1030 incorporates in a single ic all the active power, control logic and protection circuitry required for implementing, with a minimum of external components, a highly integrated isolated bias supply. the features included in the ncp1030 can result in a footprint area reduction by up to 91% compared to a solution implemented using discrete components. the ncp1030 power switch circuit is rated at 200 v, making it ideal for 48 v telecom and 42 v automotive applications. in addition, this ic can operate from an existing 12 v supply. the ncp1030 includes an extensive set of features including: ? on board power switch: eliminates the need for an external switch. as the power switch characteristics are well known the gate drive is tailored to control switching transitions and help reduce electromagnetic interference (emi). ? an internal start-up regulator: provides power to the ncp1030 during start-up. after start-up, the regulator is disabled, thus reducing power consumption. the regulator can be powered directly from the input line. ? internal error amplifier: allows the implementation of an isolated supply using primary side regulation without the need for an optocoupler. ? internal cycle by cycle current limit: eliminates the need for external sensing components. the programmed current limit is 500 ma. ? proprietary active leading edge blanking (leb) circuit: provides better current limit control compared to a fixed blanking period. the active leb circuit masks the current signal during the power switch turn on transition. ? individual line undervoltage and overvoltage (uv/ov) detectors with hysteresis: eliminate the need for external supervisory function. the uv/ov detectors can be disabled if not needed. ? single capacitor oscillator: eliminates traditional timing resistor. oscillator is optimized for operation up to 1.0 mhz. ? internal 2% voltage reference: eliminates the need for an external bypass capacitor. ? thermal shutdown circuit: protects the device in the event the maximum junction temperature is exceeded. design specifications an isolated bias supply for a telecom system is designed and implemented using the ncp1030. the supply delivers 2.0 w at 12 v. the converter specifications are listed in table 1. table 1. bias supply specifications parameter symbol min max input voltage v in 35 v 76 v frequency 250 khz 300 khz peak efficiency 80% - output voltage v out 10.8 v 13.2 v output current i out 0.017 a 0.17 a output power p out 2.0 w - a flyback topology operating in discontinuous mode is selected because of its simplicity and low part count. application note http://onsemi.com
and8119/d http://onsemi.com 2 flyback converter a dual output flyback converter is shown in figure 1. output 1 is regulated by means of output 2, providing an isolated output 1 without the need for an optocoupler. figure 1. isolated flyback converter tx d2 + - r2 + - ea pwm controller + - + - d1 + - r1 m1 snubber v in c out v out (output1) c cc v cc (output2) v ref current flows in the primary side when the power switch, m1, is on. the transformer primary side dot end becomes positive with respect to the non-dot end. while the power switch is on, energy is stored in the transformer and d1 and d2 are reverse biased. when m1 turns off, the transformer winding polarities are reversed, forward biasing d1 and d2. energy is transferred to the secondary outputs during this period. if the secondary current decays to zero before the switch turns on again, the converter operates in discontinuous mode. otherwise, it operates in continuous mode. the converter regulates the output by sampling the output voltage and comparing it to a reference voltage. a signal proportional to their difference is generated and used to adjust the on time of m1 such that the voltage dif ference is reduced. the snubber limits the voltage across the power switch and helps reduce noise. design procedure the converter is designed to operate at a maximum duty cycle (dc) of 40 % and a primary peak current (i ppk ) of 400 ma. the required primary inductance, l p , is calculated using equation 1. l p v in(min) dc i ppk (eq. 1) solving equation 1, a primary inductance of 127 h is required. the transformer turns ratio np ns is calculated using equation 2 n p n s (v in (i ppk r ds(on) )) dc (v out v d1) (0.8 dc) (eq. 2) where, v ?d1 is the forward voltage drop across d1 and r ds(on) is the power switch on resistance. equation 2 relates the on-time volt-second product to the reset volt-second product and adds a 20% dead time to insure the converter operates in discontinuous mode. solving equation 2 assuming a 0.5 v drop across d1, n p n s (35 v (0.4 a 7 )) 0.4 (12 v 0.5 v) (0.8 0.4) (eq. 3) a turns ratio greater than 2.58 is required. a turns ratio of 2.78 is selected. a maximum stress voltage of 110 v across the primary switch during the turn off period is calculated using equation 4. v stress v in(max) n p n s (v out v d1) (eq. 4) the voltage is significantly below the 200 v maximum rating of the ncp1030 internal power switch. the transformer winding arrangement includes a split primary with bifilar secondaries. the transformer can be ordered from coilcraft under part number b0226-e . table 2 summarizes the specifications of the transformer. table 2. transformer specifications parameter terminals min max magnetizing inductance @ 0.4 a 1,2-3,4 102 h - leakage inductance 1,2-3,4 - 0.955 h dc resistance 1-4 2-3 5-6 7-8 - - - - 0.655 0.82 0.248 0.248 resonant frequency - 3.8 mhz (typ.) main output two main factors, voltage ripple and frequency compensation, are considered for the selection of the output capacitor, c out . this section will focus on voltage ripple, while frequency compensation is covered in a latter section. the output capacitor provides the load current during the switch on time. if the target voltage droop is known, c out is calculated using equation 5. c out i out (1 dc) v droop (eq. 5) solving equation 5, a maximum voltage droop of 50 mv requires a 7.4 f capacitor. however, c out may be increased to facilitate frequency compensation. the secondary peak current, i spk , and the diode blocking voltage, v block , determine the selection of rectification diodes, d1 and d2. the primary peak current and transformer turns ratio determine the secondary peak current as given by equation 6. i spk i ppk n p n s (eq. 6)
and8119/d http://onsemi.com 3 the voltage across the rectification diode is given by equation 7. v block v out v in(max) n s n p (eq. 7) solving equations 6 and 7, the rectification diode needs to handle 1.11 a and 39.34 v. in addition to the voltage calculated using equation 7, voltage spikes during switching transitions need to be considered when selecting the blocking voltage rating. a schottky diode is selected to reduce the forward voltage drop, thus reducing power dissipation. on semiconductor ? s mbra160 is selected as it meets all the requirements. auxiliary supply regulator the auxiliary supply (output 2) provides a means to regulate the main output (output 1). in addition, the auxiliary winding disables the internal start-up circuit and provides power to the ncp1030 after initial power up. the same turns ratio and rectification diode used for the main output are used for the auxiliary winding to improve voltage tracking between the outputs. the auxiliary winding capacitor, c cc , is selected such that a voltage greater than 7.5 v is maintained on the v cc pin while the output reaches regulation. the time the output reaches regulation is measured at 0.8 ms. once the start-up time is known, c cc is calculated using equation 8. c cc i cc t 2.5 v (eq. 8) where, i cc includes the ncp1030 bias current (i cc3 ) and any additional current supplied by c cc . assuming an i cc3 of 3.0 ma and a 2.0 ma bias current for the feedback sensing resistors, c cc is calculated at 1.6 f. the v cc capacitor is set at 2.2 f. please note that if c cc is increased to match c out , the transient response of the converter will suffer. this is because the capacitance to current ratio of the auxiliary winding is significantly greater then the output winding, taking it longer for c cc to follow c out during a transient condition. feedback loop if the feedback loop is not stable, the converter will oscillate. to insure the loop is stable, the open loop frequency response needs to cross 0 db at a slope of -20 db/dec, with a phase margin above 45 under all line and load conditions. this is accomplished by shaping the loop response using the internal error amplifier (ea). the block diagram shown in figure 2 is used to evaluate the converter open loop response. figure 2. flyback converters tx d2 + - ea pwm controller + - a + - d1 + - z1 b v in c out r out v out r esr c out(eq) r out(eq) ncp1030 v ref zf r bias the open loop frequency response of the system (from a to b) is approximated by the modulator gain and the output network frequency response. additional high frequency components are present but are not considered for our analysis as they are far beyond the crossover frequency. the modulator gain, g mod , is approximated by equation 9. g mod 3 2 v in r out(eq) 2 f l p (eq. 9) the output network block is comprised of c out , r esr and r out . the frequency response of the output network is given by equation 10. h( ) sr esr c out(eq) 1 sc out(eq) (r esr r out(eq) ) 1 (eq. 10) the total open loop frequency response is the product of equations 9 and 10. please note that c out(eq) includes c cc and c out reflected to the auxiliary winding by the transformer turns ratio. as the same turns ratio is used for both the auxiliary and output windings, c out adds directly to c cc . the output network has one zero and one pole and they are given by equations 11 and 12, respectively. z1 1 2 c out r esr (eq. 11) p1 1 2 r out c out (eq. 12) the modulator gain response depends on v in . two extreme conditions, both minimum r out and input voltage (g mod1 ) as well as both maximum r out and input voltage (g mod2 ) are considered for frequency compensation. in order to facilitate frequency compensation, c out is increased to 22 f. the simulated open loop frequency responses for g mod1 and g mod2 are shown in figures 3 and 4, respectively.
and8119/d http://onsemi.com 4 figure 3. open loop frequency response for g mod1 -50 -40 -30 -20 -10 0 10 20 30 40 50 frequency (hz) magnitude (db) -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 angle (degrees) 10 1 10 2 10 3 10 4 10 5 10 6 magnitude phase figure 4. open loop frequency response for g mod2 10 1 10 2 10 3 10 4 10 5 10 6 -50 -40 -30 -20 -10 0 10 20 30 40 50 frequency (hz) magnitude (db) -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 angle (degrees) magnitude phase the frequency compensation can be achieved using a type ii error amplifier (ea) as the one shown in figure 5. figure 5. type ii error amplifier + - + - c2 r7 c6 r6 r4 zf z1 input output (r5) ea i bias1 r bias v ref a type ii error amplifier has 2 poles and 1 zero. the transfer function is given by equation 13. h( ) sr 7 c 2 1 sr 4 (c 2 c 6 ) 1 sr 7 c 7 c 6 c 7 c 6 (eq. 13) one of the poles, f p2 , is at the origin. the frequency of the remaining pole and zero are given by equations 14 and 15, respectively. z2 1 2 r 7 c 2 (eq. 14) p3 (c 2 c 6 ) 2 r 7 c 2 c 6 (eq. 15) the ea poles and zero locations are selected to achieve the desired crossover frequency, f co . a system crossover frequency of 10 khz is selected for g mod1 . as the modulator gain depends on the input voltage, a higher f co is obtained for the maximum input voltage condition with equivalent output load. the selection of the compensation components begins by noting that the voltage on the v fb pin should be equal to 2.5 v (v ref ) when the output is in regulation (12 v). if the feedback sensing resistor network bias current (i bias1 ) is known, r 4 and r 5 are calculated using equations 16 and 17, respectively. r 5 v ref i bias1 (eq. 16) r 4 v cc i bias1 r 5 (eq. 17) using a bias current of 2.0 ma, r 4 and r 5 are calculated at 4.99 k and 1.30 k , respectively. resistor r 6 provides a test point to measure the open loop frequency response. it is set at 10 to avoid disrupting the dc bias point. the error amplifier dc gain, g ea , is calculated using equation 18. it is set at 6.03 db to achieve a gain of 0 db at 10 khz for g mod1 . g ea 20 log r 7 r 4 (eq. 18) the error amplifier zero, f z2 , is placed before the system response crosses 0 db. pole, f p3 , is placed after f co to attenuate high frequency components. table 3 summarizes the system gain, poles and zeros. figure 6 shows the ea frequency response. table 3. system gain, poles and zeros parameter frequency (khz) magnitude (db) f p1 (@ g mod1 ) 0.091 - f p1 (@ g mod2 ) 0.009 - f p2 0 - f p3 23.9 - f z1 77.4 - f z2 0.482 - g ea - 6.03
and8119/d http://onsemi.com 5 figure 6. error amplifier frequency response 10 1 10 2 10 3 10 4 10 5 10 6 -40 -30 -20 -10 0 10 20 30 40 50 60 frequency (hz) magnitude (db) -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 angle (degrees) magnitude phase the phase contributions of a zero and a pole at the crossover frequency are given by equations 19 and 20, respectively. z tan -1 co z (eq. 19) p tan -1 co p (eq. 20) the phase margin, m , is evaluated taking into account the phase contribution of all the poles and zeros as shown below in equation 21. m 180 p1 p2 p3 z1 z2 (eq. 21) m 180 89.5 90 22.7 7.33 87.24 72.4 the calculated phase margin is 72.4 . the 180 term arises because the ea is in an inverting configuration. the simulated system frequency responses for g mod1 and g mod2 are shown in figure 7. 10 1 10 2 10 3 10 4 10 5 10 6 -20 -10 0 10 20 30 40 50 60 70 80 frequency (hz) magnitude (db) -180 -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 angle (degrees) magnitude (vin = 36v, rout = 72 ) phase (vin = 36v, rout = 72 ) magnitude (vin = 76v, rout = 720 ) phase (vin = 76v, rout = 720 ) figure 7. system frequency response under/overvoltage detectors the ncp1030 eliminates the need for additional supervisory circuitry by incorporating individual under and overvoltage detectors with hysteresis. the controller is enabled if the voltage on the uv pin is above 2.5 v and the voltage on the ov pin is below 2.5 v. the uv/ov detectors can be biased using an external resistor divider as shown in figure 8. figure 8. uv/ov resistor bias network r1 + - r2 r3 + - c7 c8 v in i bias2 v uv v ov if the resistor network bias current, i bias2 , is known, and the v ov and v uv thresholds are equal, r 1 , r 3 and r 2 are calculated using equations 22, 23 and 24, respectively. r 1 v in(max) i bias2 (eq. 22) r 3 v ov r 1 v in(min) v in(min) v in(max) v ov ( v in v in(min) ) (eq. 23) r 2 r 3 v in v in(min) (eq. 24) using a bias current of 78 a, a turn on voltage of 35 v, a turn off voltage of 80 v and a v ov threshold of 2.55 v, r 1 , r 2 and r 3 are calculated at approximately 1.0 m , 45.3 k and 34 k , respectively. capacitors c 7 and c 8 help reduce noise and provide a stable voltage during turn on and turn off transitions. they are set at 10 nf. oscillator frequency an oscillator frequency of 275 khz is obtained with a timing capacitor (c t ) of 680 pf. the tolerance of c t is set at 5%. snubber an rcd snubber as shown in figure 9 is added to help reduce noise. the snubber is returned to the positive supply rail to reduce the voltage stress on c 9 to v in . if returned to the negative supply rail, the voltage stress is 2v in .
and8119/d http://onsemi.com 6 figure 9. rcd snubber tx d3 r9 c9 v in + - the power dissipation of r 9 is determined by c 9 and is given by equation 25. (eq. 25) p 1 2 c 9 v in 2 the snubber components are not assembled in the converter. however, electrical connections are provided if the user wants to add the snubber components. input filter an l-c filter at the converter input is used to reduce emi. the input l-c filter reduces noise and provides a solid input voltage to the converter. the filter is shown in figure 10. capacitor c 10 is used for common mode noise reduction. figure 10. input l-c filter schematic l1 c5 2.2 + - c10 0.022 v in 2.2 h oscillation may occur if the converter input impedance, z in , is lower than the lc filter output impedance [1] . the converter input impedance can be approximated as a negative resistor using equation 26. z in (db ohm) - 20 log v out i out (eq. 26) the converter closed loop input impedance is ultimately determined by the converter feedback loop as well as the open loop input impedance. however, a resistor is a good approximation and will be used for our analysis. figure 11 shows the theoretical input filter output impedance and the approximated converter input impedance. figure 11. lc filter output impedance and approximated converter input impedance lc filter output impedance converter input impedance 40 30 20 10 0 -10 -20 -30 -40 10 2 10 3 10 4 10 5 10 6 frequency (hz) magnitude (db) layout considerations switching regulators can be noisy! however, with careful layout, noise is reduced. a few things to remember are: 1. keep switching elements and high current traces away from the controller and sensitive nodes. 2. keep trace lengths to a minimum, especially important for high current paths and timing components. 3. use wide traces for high current paths. 4. place bypass capacitors close to the components. 5. use a ground plane if possible or a single point ground system. the bias supply is built using a single layer fr4, board. the board size is 2.0 in x 3.5 in. the complete circuit schematic is shown in figure 12 and an actual size picture of the board is shown in figure 13. the bill of material is listed in table 4. figure 12. complete circuit schematic gnd comp + 35-76v - vcc vdrain uv ov ct vfb + - 22 mbra160t3 mbra160t3 2.2 1m 10 4k99 1k30 10k 0.033 680p 680p 0.01 0.01 2.2 2.2 1:2.78 45k3 34k 12v ncp1030 0.022 100 p mura110t3 499
and8119/d http://onsemi.com 7 figure 13. demonstration board (actual size) table 4. bill of materials ref value vendor part number c1 680 pf vishay vj0805a681jxa c2 0.033 f vishay vj0805y333kxxa c3 22 f tdk c4532x5r1e226m c4 2.2 f tdk c4532x7r1h225m c5 2.2 f tdk c4532x7r2a225m c6 680 pf vishay vj0805a681jxa c7, c8 0.01 f vishay vj0805y103kxxat c9 100 pf tdk c1608c0g2e101j c10 0.022 f tdk c2012x7re223k d1, d2 - on semiconductor mbra160t3 d3 - on semiconductor mura110t3 j1-j4 - mill-max terminal l1 2.2 h vishay imc-1210 r1 1 m vishay crcw08051004f r2 45.3 k vishay crcw08054532f r3 34 k vishay crcw08053402f r4 4.99 k vishay crcw08054991f r5 1.30 k vishay crcw08051301f r6 10 vishay crcw080510r0f r7 10 k vishay crcw08051002f r8 0 vishay crcw0805000zj r9 499 vishay crcw12104990f tx1 - coilcraft b0226-e u1 - on semiconductor ncp1030dr2 design verification the final step in our design includes validation and test of the bias supply. before powering the supply, it should be inspected for potential problems. a few suggestions include: 1. verify all connections. check for shorts and opens, especially on the input and output terminals. 2. verify component values. 3. slowly increase the input voltage while monitoring the input current. if the input current exceeds 10 ma, repeat steps 1 to 3. 4. once the input voltage reaches 25 v, measure the voltage on critical nodes. the ncp1030 start-up regulator should be on. if the voltages are not correct, remove power and repeat steps 1 to 3. 5. increase the input voltage to 36 v. measure the output voltage. if it is not approximately 12 v, repeat steps 1 to 3. 6. increase the input voltage above 80 v. the output should turn off. please be careful when probing and testing the converter. high voltage may be present. exercise caution! once the converter functionality is verified, the board performance is evaluated and compared to our original goals. the evaluation criteria includes: 1. open loop frequency response. 2. efficiency. 3. line and load regulation. 4. step load response. 5. start-up response. the open loop response is measured injecting an ac signal across r 6 using a network analyzer as shown in figure 14.
and8119/d http://onsemi.com 8 figure 14. open loop frequency response measurement set-up d2 + - z1 1:1 r6 network analyzer ref a b to converter to error amplifier c cc v cc r bias the measured frequency response is shown in figure 15. the crossover frequency is measured at 9 khz. figure 15. open loop frequency response 50 magnitude (db) 40 30 20 10 0 -10 -20 -30 -40 -50 10 2 10 3 10 4 10 5 10 6 frequency (hz) v in = 36 v r out = 72 peak efficiency is measured at 83%. figure 16 shows the efficiency vs. output current under several input voltage conditions. figure 16. efficiency vs output current i out , output current (ma) 125 85 50 70 25 0 , efficiency (%) 60 90 65 75 80 200 75 100 150 175 v in = 36v v in = 48v v in = 76v line and load regulation are calculated using equations 27 and 28, respectively. reg line v out v in (eq. 27) reg load v out(no load) v out(full load) v out(no load) (eq. 28) line regulation is measured below 0.5% and load regulation is measured below 8%. figure 17 shows the output voltage variation to output current under several input voltage conditions. figure 17. output voltage vs. output current i out , output current (ma) 125 11.9 50 11.2 25 0 v out , output voltage (v) 11.0 12.0 11.1 11.7 11.8 200 75 100 150 175 11.3 11.4 11.5 11.6 v in = 36v v in = 48v v in = 76v the dynamic response of the converter is evaluated stepping the load current from 50% to 75% and from 75% to 50% of i out(max) . the step load transient responses are shown in figures 18 and 19. figure 18. output voltage response to a step load from 87 ma to 127 ma v in = 48 v v out = 11.6 v 50 ms/div v out , output voltage (50 mv/div) i out , output current (20 ma/div) i out = 87 ma
and8119/d http://onsemi.com 9 figure 19. output voltage response to a step load from 127 ma to 87 ma v in = 48 v i out = 127 ma v out = 11.45 v 50 ms/div v out , output voltage (50 mv/div) i out , output current (20 ma/div) output voltage ripple is measured at 25 mv for an output current of 170 ma. it is significantly below the 50 mv target. the output voltage ripple waveform is shown in figure 20. v in = 48 v v out = 11.33 v 2.0 s/div v out , output voltage (20 mv/div) figure 20. output voltage ripple i out = 170 ma finally, the converter turn on response at full load is evaluated. figure 21 shows the output turn on transient response at full load. output2 1.0 ms/div v out , output voltage (2.0 v/div) figure 21. output voltage during turn on at full load i out = 170 ma output1 (isolated) 0 v dss operation output 2 operates in dss while the converter is disabled. once the converter is enabled, output 1 tracks output 2. summary an isolated 12 v bias supply for a 48 v telecom system is implemented using the ncp1030. the converter achieves a peak efficiency of 83% while providing good transient response. references 1. ridley, ray. ? the evolution of power electronics ?? , switching power magazine , fall 2001:16-30. 2. pressman, abraham i. switching power supply design. 2nd ed. new york, ny: macgraw hill.
and8119/d http://onsemi.com 10 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 2-9-1 kamimeguro, meguro-ku, tokyo, japan 153-0051 phone : 81-3-5773-3850 on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. and8119/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303-675-2175 or 800-344-3860 toll free usa/canada fax : 303-675-2176 or 800-344-3867 toll free usa/canada email : orderlit@onsemi.com n. american technical support : 800-282-9855 toll free usa/canada
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